Design a verilog model of a half adder and write a testbench to verify the designed verilog model.
p9. 半加法器設計電路
module Add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor (sum,a,b);
nand (c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule
module test;
reg a,b;
wire sum,c_out;
Add_half U0 (sum,c_out,a,b);
initial
begin a = 0;b=0;
#10 a =0; b = 1;
#10 a =1; b = 0;
#10 a =1; b = 1;
#10 $finish;
end
endmodule
p9. 半加法器設計電路
module Add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor (sum,a,b);
nand (c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule
module test;
reg a,b;
wire sum,c_out;
Add_half U0 (sum,c_out,a,b);
initial
begin a = 0;b=0;
#10 a =0; b = 1;
#10 a =1; b = 0;
#10 a =1; b = 1;
#10 $finish;
end
endmodule
1 則留言:
module Add_full(sum,c_out,a,b,c_in)
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
Add_half M1(w1,w2,a,b);
Add_half M2(sum,w3,w1,c_in);
or (c_out,w2,w3);
endmodule
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